example code for R/W 2232H sync FIFO + FPGA?

[r***@agilent.com]

Hi libftdi developers,


I'm working on a 200Mb/s ring network built out of lattice FPGA chips using oversampled clock and data recovery.


I'd like to communicate with the master node using an FTDI 2232H synchronous FIFO. Basically, I'd like to burst command packets into the master node (a sequence of bytes), and then check for and receive any reply bytes as available. The peak throughput of the network is 100mb/s, but I'd be happy to do 1/4 of that.


I found a promising open source verilog for the FPGA side: https://github.com/6thimage/FT245_interface

<https://github.com/6thimage/FT245_interface>


<https://github.com/6thimage/FT245_interface>

Is there a known working example code for reading/writing from a synchronous USB2.0 chip? The example in the source code is read only with (as near as I can tell) issues on writing. I'd like the speed of synchronous, but I'd be willing to start with asynch if that works too.


kind regards,

--

Rick Walker


________________________________
From: libftdi+***@developer.intra2net.com <libftdi+***@developer.intra2net.com>
Sent: Wednesday, November 8, 2017 6:07 PM
To: WALKER,RICK (A-Santa Clara,ex1)
Subject: Welcome to ***@developer.intra2net.com

Welcome! You have been subscribed to the

***@developer.intra2net.com

mailinglist.

To unsubscribe send a message to:

libftdi+***@developer.intra2net.com

And for help send a message to:

libftdi+***@developer.intra2net.com




--
libftdi - see http://www.intra2net.com/en/developer/libftdi for details.
To unsubscribe send a mail to libftdi+***@developer.intra2net.com

[Hawkins, David W (334B)]

Hi Rick,

Here's my analysis (including interface FSMs and block diagrams)
https://www.ovro.caltech.edu/~dwh/correlator/pdf/ftdi.pdf
https://www.ovro.caltech.edu/~dwh/correlator/pdf/ftdi_spi.pdf

The FT2232H can easily burst at 60MB/s. The doc has SignalTap II traces demonstrating it.

I wrote the original code in VHDL for Altera devices (using their counter primitives and so on). Since you're targeting Lattice devices it might be easier to code it from scratch (the FSMs can be re-coded from the ASM charts in the document - I create those before writing VHDL or SystemVerilog code).

If I needed this interface now, I'd code it in SystemVerilog and replace the Avalon-ST interface with the AXI4-Stream interface (which is literally identical, but does not use the start-of-packet flag).

If you want the VHDL code, just ask ... and I'll try to be more organized and put it on github :)

Cheers,
Dave

From: ***@agilent.com<mailto:***@agilent.com> [mailto:***@agilent.com]
Sent: Wednesday, November 08, 2017 6:20 PM
To: ***@developer.intra2net.com<mailto:***@developer.intra2net.com>
Subject: example code for R/W 2232H sync FIFO + FPGA?


Hi libftdi developers,



I'm working on a 200Mb/s ring network built out of lattice FPGA chips using oversampled clock and data recovery.



I'd like to communicate with the master node using an FTDI 2232H synchronous FIFO. Basically, I'd like to burst command packets into the master node (a sequence of bytes), and then check for and receive any reply bytes as available. The peak throughput of the network is 100mb/s, but I'd be happy to do 1/4 of that.



I found a promising open source verilog for the FPGA side: https://github.com/6thimage/FT245_interface


<https://github.com/6thimage/FT245_interface>

Is there a known working example code for reading/writing from a synchronous USB2.0 chip? The example in the source code is read only with (as near as I can tell) issues on writing. I'd like the speed of synchronous, but I'd be willing to start with asynch if that works too.



kind regards,

--

Rick Walker

________________________________
From: libftdi+***@developer.intra2net.com<mailto:libftdi+***@developer.intra2net.com> <libftdi+***@developer.intra2net.com<mailto:libftdi+***@developer.intra2net.com>>
Sent: Wednesday, November 8, 2017 6:07 PM
To: WALKER,RICK (A-Santa Clara,ex1)
Subject: Welcome to ***@developer.intra2net.com<mailto:***@developer.intra2net.com>

Welcome! You have been subscribed to the

***@developer.intra2net.com<mailto:***@developer.intra2net.com>

mailinglist.

To unsubscribe send a message to:

libftdi+***@developer.intra2net.com<mailto:libftdi+***@developer.intra2net.com>

And for help send a message to:

libftdi+***@developer.intra2net.com<mailto:libftdi+***@developer.intra2net.com>

________________________________

libftdi - see http://www.intra2net.com/en/developer/libftdi for details.
To unsubscribe send a mail to libftdi+***@developer.intra2net.com<mailto:libftdi+***@developer.intra2net.com>



--
libftdi - see http://www.intra2net.com/en/developer/libftdi for details.
To unsubscribe send a mail to libftdi+***@developer.intra2net.com

[Uwe Bonnes]

Hawkins,> Hi Rick, Here?s my analysis (including interface FSMs and
Hawkins,> block diagrams)

Hawkins,> https://www.ovro.caltech.edu/~dwh/correlator/pdf/ftdi.pdf

Hawkins,> https://www.ovro.caltech.edu/~dwh/correlator/pdf/ftdi_spi.pdf



Hawkins,> The FT2232H can easily burst at 60MB/s. The doc has SignalTap
Hawkins,> II traces demonstrating it.

Did you have a look at example/stream_test

We use that code since years to stream high speed ADC data.

Bye

[Salvador Eduardo Tropea]

Here is an announcement by Marc Pignat.
I tried the ft2tcp code successfully, you can also take a look at SigRok
library, it has Async and Sync FIFO exampes, used for logic analyzer
modules.
The trick is to configure the FT2232H EEPROM to define the channels as
FIFO. Then the soft can enable the Sync FIFO mode, you can verify it
with the FT2232H CLKOUT signal (starts to send 60 MHz as soon as the
chip enters in Sync FIFO mode).

<--- Marc mail
Dear libftdi community,



I'm using the libftdi library to communicate with a ftdi chip in ft245
synchronous fifo mode.

I have mostly tested the download (ftdi to host direction), and I have
some great bandwidth : 48.6 MB/s !
(48.6 MB/s comes from dd and dd probably uses 1MB = 10^6 bytes, not
1024*1024)

I would like to share with you my C/C++ and VDHL code.

* https://github.com/RandomReaper/ft2tcp
        This sofware connects to a ftdi chip, configure it in
synchronous fifo mode
        and make the (bidirectional) stream available on a TCP socket.

* https://github.com/RandomReaper/pim-vhdl
        This is my VHDL library, including the ft245 synchronous
interface (hdl/rtl/ft245_sync_if/ft245_sync_if.vhd)
        and some examples using it
(board/mimas/projects/ft245_counter_to_host for the bandwidth test).

The hardware has been tested on:
        * Xilinx Spartan 6 (XC6SLX9) + ft2232h
        * Actel igloo (I forget the model name) + ft2232h

The software has been tested on:
        * Ubuntu 16.10 LTS AMD64 bits on a core-i7 (download speed :
48.6 MB/s).
        * Windows 7 64 bits (download speed : 38.9 MB/s).
        * raspbian on a raspberry pi 2b (download speed : 36.6 MB/s).
        * Ubilinux on an intel edison (download speed around 15 MB/s).


Thank you for your great work!


Best regards


Marc
<----

Post by r***@agilent.com
Hi libftdi developers,
I'm working on a 200Mb/s ring network built out of lattice FPGA chips
using oversampled clock and data recovery.
I'd like to communicate with the master node using an FTDI 2232H
synchronous FIFO.  Basically, I'd like to burst command packets into
the master node (a sequence of bytes), and then check for and receive
any reply bytes as available.  The peak throughput of the network is
100mb/s, but I'd be happy to do 1/4 of that.
https://github.com/6thimage/FT245_interface
<https://github.com/6thimage/FT245_interface>
<https://github.com/6thimage/FT245_interface>
Is there a known working example code for reading/writing from a
synchronous USB2.0 chip?  The example in the source code is read only
with (as near as I can tell) issues on writing.  I'd like the speed of
synchronous, but I'd be willing to start with asynch if that works too.
kind regards,
--
Rick Walker
------------------------------------------------------------------------
*Sent:* Wednesday, November 8, 2017 6:07 PM
*To:* WALKER,RICK (A-Santa Clara,ex1)
Welcome! You have been subscribed to the
mailinglist.
------------------------------------------------------------------------
*libftdi* - see http://www.intra2net.com/en/developer/libftdi for details.
To unsubscribe send a mail to

--
Ing. Salvador Eduardo Tropea http://utic.inti.gob.ar/
INTI - Micro y Nanoelectrónica (CMNB) http://www.inti.gob.ar/
Unidad Técnica Sistemas Inteligentes Av. General Paz 5445
Tel: [phone] ext. 6919 San Martín - B1650KNA
FAX: [phone] Buenos Aires * Argentina





--
libftdi - see http://www.intra2net.com/en/developer/libftdi for details.
To unsubscribe send a mail to libftdi+***@developer.intra2net.com